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MCQs

Total Questions : 457 | Page 6 of 46 pages
Question 51. The inverter is ___________
  1.    None of these
  2.    AND gate
  3.    OR gate
  4.    NOT gate
 Discuss Question
Answer: Option D. -> NOT gate
Question 52. What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view?
  1.    Tristate output operation
  2.    Input operation
  3.    Bi-directional I/O pin access
  4.    All of these
 Discuss Question
Answer: Option D. -> All of these
Question 53. An AND gate will function as OR if
  1.    All the inputs to the gates are “1”
  2.    Either of the inputs is “1”
  3.    All the inputs are ‘0’
  4.    All the inputs and outputs are complemente'
 Discuss Question
Answer: Option D. -> All the inputs and outputs are complemente'
Question 54. Assuming 8 bits for data, 1 bit for parity, I start bit and 2 stop bits, the number of characters that 1200 BPS communication line can transmit is.
  1.    None of these
  2.    120 CPS
  3.    10 CPS
  4.    12 CPS
 Discuss Question
Answer: Option D. -> 12 CPS
Question 55. The NAND gate is AND gate followed by ___________.
  1.    None of these
  2.    AND gate
  3.    OR gate
  4.    NOT gate
 Discuss Question
Answer: Option D. -> NOT gate
Question 56. The NOR gate is OR gate followed by ___________.
  1.    NOT gate
  2.    NAND gate
  3.    AND gate
  4.    None of these
 Discuss Question
Answer: Option A. -> NOT gate
Question 57. Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?
  1.    PGA
  2.    PLCC
  3.    BGA
  4.    QFP
 Discuss Question
Answer: Option C. -> BGA
Question 58. A hexadecimal odometer displays F 52 F. The next reading will be
  1.    G52F
  2.    F53F
  3.    F52E
  4.    F53O
 Discuss Question
Answer: Option D. -> F53O
Question 59. A NAND gate is called a universal logic element because
  1.    Many digital computers use NAND gates.
  2.    Any logic function can be realized by NAND gates alone
  3.    It is used by everybody
  4.    All the minization techniques are applicable for optimum NAND gate realization
 Discuss Question
Answer: Option B. -> Any logic function can be realized by NAND gates alone
Question 60. The binary code of (21.125)10 is
  1.    10101.01
  2.    10100.111
  3.    10101.001
  4.    10100.001
 Discuss Question
Answer: Option C. -> 10101.001

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