Question 41. The procedure given below is required to find and replace certain characters inside an input character string
supplied in array A. The characters to be replaced are supplied in array oldc, while their respective
replacement characters are supplied in array newc. Array A has a fixed length of five characters, while
arrays oldc and newc contain three characters each. However, the procedure is flawed. void find_and_replace (char *A, char *oldc, char *newc) {             for (int i=0; i

Question 42. A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?

Question 43. A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?

Question 44. In an IPv4 datagram, the M bit is 0, the value of HLEN is 10, the value of total length is 400 and the fragment offset value is 300. The position of the datagram, the sequence numbers of the first and the last bytes of the payload, respectively are

Question 45. Consider the following two sets of LR(1) items of an LR(1) grammar.X → c.X, c/d     X → c.X, $X → .cX, c/d     X →.cX, $X → .d, c/d       X →.d, $Which of the following statements related to merging of the two sets in the corresponding LALR parser is/are FALSE?1. Cannot be merged since look aheads are different.2. Can be merged but will result in S-R conflict.3. Can be merged but will result in R-R conflict.4. Cannot be merged since go to on c will lead to two different sets.

Question 46. Which of the following is/are undecidable?

1. G is a CFG. Is L(G) = Φ?

2. G is a CFG. Is L(G) = Σ*?

3. M is a Turing machine. Is L(M) regular?

4. A is a DFA and N is an NFA. Is L(A) = L(N)?

Question 47. The preorder traversal sequence of a binary search tree is 30, 20, 10, 15, 25, 23, 39, 35, 42. Which one of the following is the postorder traversal sequence of the same tree?

Question 48. A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is

Question 49. The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.c = a + b;d = c * a;e = c + a;x = c * c;if (x > a) {     y = a * a;}else {      d = d * d;      e = e * e;}Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?

Question 50. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, ...., I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is