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MCQs

Total Questions : 133 | Page 1 of 14 pages
Question 1.  
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
  1.    10.24 kHz
  2.    5 kHz
  3.    30.24 kHz
  4.    15 kHz
 Discuss Question
Answer: Option B. -> 5 kHz
Question 2.  Propagation delay time, tPLH, is measured from the ________.
  1.    triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
  2.    triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
  3.    preset input to the LOW-to-HIGH transition of the output
  4.    clear input to the HIGH-to-LOW transition of the output
 Discuss Question
Answer: Option A. -> triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
Question 3.  Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?
  1.    The logic level at the D input is transferred to Q on NGT of CLK.
  2.    The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
  3.    The Q output is ALWAYS identical to the D input when CLK = PGT.
  4.    The Q output is ALWAYS identical to the D input.
 Discuss Question
Answer: Option A. -> The logic level at the D input is transferred to Q on NGT of CLK.
Question 4.  How many flip-flops are in the 7475 IC?
  1.    1
  2.    2
  3.    4
  4.    8
 Discuss Question
Answer: Option C. -> 4
Question 5.  How many flip-flops are required to produce a divide-by-128 device?
  1.    1
  2.    4
  3.    6
  4.    7
 Discuss Question
Answer: Option D. -> 7
Question 6.  Which is not an Altera primitive port identifier?
  1.    clk
  2.    ena
  3.    clr
  4.    prn
 Discuss Question
Answer: Option C. -> clr
Question 7.  How is a J-K flip-flop made to toggle?
  1.    J = 0, K = 0
  2.    J = 1, K = 0
  3.    J = 0, K = 1
  4.    J = 1, K = 1
 Discuss Question
Answer: Option D. -> J = 1, K = 1
Question 8.  The timing network that sets the output frequency of a 555 astable circuit contains ________.
  1.    three external resistors are used
  2.    two external resistors and an external capacitor are used
  3.    an external resistor and two external capacitors are used
  4.    no external resistor or capacitor is required
 Discuss Question
Answer: Option B. -> two external resistors and an external capacitor are used
Question 9. . Which of the following is correct for a gated D flip-flop?
  1.    The output toggles if one of the inputs is held HIGH.
  2.    Only one of the inputs can be HIGH at a time.
  3.    The output complement follows the input when enabled.
  4.    Q output follows the input D when the enable is HIGH.
 Discuss Question
Answer: Option D. -> Q output follows the input D when the enable is HIGH.
Question 10.  The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
  1.    parity error checking
  2.    ones catching
  3.    digital discrimination
  4.    digital filtering
 Discuss Question
Answer: Option B. -> ones catching

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