Sail E0 Webinar

MCQs

Total Questions : 81 | Page 6 of 9 pages
Question 51.  When testing an n-channel D-MOSFET, resistance G to D = , resistance G to S = , resistance D to SS = and 500 , depending on the polarity of the ohmmeter, and resistance D to S = 500 . What is wrong?
  1.    short D to S
  2.    open G to D
  3.    open D to SS
  4.    nothing
 Discuss Question
Answer: Option D. -> nothing
Question 52.  A MOSFET has how many terminals?
  1.    2 or 3
  2.    3
  3.    4
  4.    3 or 4
 Discuss Question
Answer: Option D. -> 3 or 4
Question 53. . JFET terminal "legs" are connections to the drain, the gate, and the:
  1.    channel
  2.    source
  3.    substrate
  4.    cathode
 Discuss Question
Answer: Option B. -> source
Question 54. . A very simple bias for a D-MOSFET is called:
  1.    self biasing
  2.    gate biasing
  3.    zero biasing
  4.    voltage-divider biasing
 Discuss Question
Answer: Option C. -> zero biasing
Question 55. .  With the E-MOSFET, when gate input voltage is zero, drain current is:
  1.    at saturation
  2.    zero
  3.    IDSS
  4.    widening the channel
 Discuss Question
Answer: Option B. -> zero
Question 56. . With a 30-volt VDD, and an 8-kilohm drain resistor, what is the E-MOSFET Q point voltage, with ID = 3 mA?
  1.    6 V
  2.    10 V
  3.    24 V
  4.    30 V
 Discuss Question
Answer: Option A. -> 6 V
Question 57. . What is the input impedance of a common-gate configured JFET?
  1.    very low
  2.    low
  3.    high
  4.    very high
 Discuss Question
Answer: Option A. -> very low
Question 58.  IDSS can be defined as:
  1.    the minimum possible drain current
  2.    the maximum possible current with VGS held at –4 V
  3.    the maximum possible current with VGS held at 0 V
  4.    the maximum drain current with the source shorted
 Discuss Question
Answer: Option C. -> the maximum possible current with VGS held at 0 V
Question 59. . When an input signal reduces the channel size, the process is called:
  1.    enhancement
  2.    substrate connecting
  3.    gate charge
  4.    depletion
 Discuss Question
Answer: Option D. -> depletion
Question 60. . Which JFET configuration would connect a high-resistance signal source to a low-resistance load?
  1.    source follower
  2.    common-source
  3.    common-drain
  4.    common-gate
 Discuss Question
Answer: Option A. -> source follower

Latest Videos

Latest Test Papers