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Total Questions : 97 | Page 1 of 10 pages
Question 1. Consider the following logical inferences. I1: If it rains then the cricket match will not be played. The cricket match was played. Inference: There was no rain. I2: If it rains then the cricket match will not be played. It did not rain. Inference: The cricket match was played. Which of the following is TRUE?
  1.    Both I1 and I2 are correct inferences
  2.    I1 is correct but I2 is not a correct inference
  3.    I1 is not correct but I2 is a correct inference
  4.    Both I1 and I1 are not correct inferences
 Discuss Question
Answer: Option B. -> I1 is correct but I2 is not a correct inference


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Question 2. Which of the following is TRUE?
  1.    Every relation in 3NF is also in BCNF
  2.    A relation R is in 3NF if every non-prime attribute of R is fully functionally dependent on every key of R
  3.    Every relation in BCNF is also in 3NF
  4.    No relation can be in both BCNF and 3NF
 Discuss Question
Answer: Option C. -> Every relation in BCNF is also in 3NF


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Question 3. Assuming P ≠ NP, which of the following is TRUE?
  1.    NP-complete = NP
  2.    NP-complete ∩ P = φ
  3.    NP-hard = NP
  4.    P = NP-complete
 Discuss Question
Answer: Option B. -> NP-complete ∩ P = φ


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Question 4. The worst case running time to search for an element in a balanced binary search tree with n2n elements is
  1.    Î˜ (n log n)
  2.    Î˜ (n2n)
  3.    Î˜ (n)
  4.    Î˜ (log n)
 Discuss Question
Answer: Option C. -> Θ (n)


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Question 5. A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The size of the cache tag directory is
  1.    160 Kbits
  2.    136 Kbits
  3.    40 Kbits
  4.    32 Kbits
 Discuss Question
Answer: Option A. -> 160 Kbits


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Question 6. A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The number of bits in the tag field of an address is
  1.    11
  2.    14
  3.    16
  4.    27
 Discuss Question
Answer: Option C. -> 16


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Question 7. The decimal value 0.5 in IEEE single precision floating point representation has
  1.    fraction bits of 000"¦000 and exponent value of 0
  2.    fraction bits of 000"¦000 and exponent value of −1
  3.    fraction bits of 100"¦000 and exponent value of 0
  4.    no exact representation
 Discuss Question
Answer: Option C. -> fraction bits of 100"¦000 and exponent value of 0


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Question 8. A process executes the code fork(); fork(); fork(); The total number of child processes created is
  1.    3
  2.    4
  3.    7
  4.    8
 Discuss Question
Answer: Option C. -> 7


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Question 9. The protocol data unit (PDU) for the application layer in the Internet stack is
  1.    Segment
  2.    Datagram
  3.    Message
  4.    Frame
 Discuss Question
Answer: Option C. -> Message


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Question 10. Consider the function f(x) = sin(x) in the interval x ϵ [π/4, 7π/4]. The number and location(s) of the local minima of this function are
  1.    One, at Ï€/2
  2.    One, at 3Ï€/2
  3.    Two, at Ï€/2 and 3Ï€/2
  4.    Two, at Ï€/4 and 3Ï€/2
 Discuss Question
Answer: Option D. -> Two, at π/4 and 3π/2


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